1. Field of the Invention
This invention is related to the field of processors and, more specifically, to processors that execute predicated vector instructions.
2. Description of the Related Art
Vector processors exploit data-level parallelism (DLP) by performing the same operation on multiple vector elements on an input (source) operand or operands. In some vector instruction sets, multiple vector element sizes are supported. Not only are there sometimes multiple data types (e.g. integer, floating point, etc.) supported in the vectors, but also some data types may have multiple vector element sizes.
For some operations, the execution latency of the operation is dependent upon the number of elements in the vector. In many processors, instructions are launched from the scheduler before all of the input parameters are available. In cases where an instruction is launched before the number of vector elements is known to the scheduler, the latency of the instruction will be unknown at the time of launch. This complicates the scheduling of subsequent instructions (e.g. those subsequent instructions that are dependent on the instruction with unknown latency).